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General Description
The AL3201 (SCR, or Single Chip Reverb) is a one chip reverb solution that is compact, easy to use, and yet quite powerful. Built-in DRAM eliminates the need for wide bus connections to external RAM, and the choice of built-in programs and a user programmable RAM allows instant usability or custom program design.
Features
16 internal ROM programs consisting of halls, rooms, plates, delays, chorus, flange, vocal cancel, and rotary speaker emulation. Serially programmable SRAM (Writable Control Store - WCS) for program development or dynamically changing programs Programs run at 128 instructions per word clock. (6 MIPS @ 48kHz sampling frequency.) 32k location DRAM provides over 0.68s of delay at 48kHz sampling frequency. Internal crystal oscillator circuit eliminates need for discrete external passive components. Internal voltage regulators allow operation at both 5V and 3.3V VDD. Internal 1000pF bypass capacitor to reduce voltage swings at the rails.
Applications
Personal stereos with reverb functions. Extremely portable guitar effects boxes. Karaoke machines utilizing the vocal cancel program. Hardware reverb effects for computer sound cards. Ambience settings for car stereos.
Int/Ext XtalIn XtalOut Prog0/SData Prog1/SClk Prog2 Prog3
16
DigOut
DigIn VDD Bypass Gnd Reset SysClk BitClk WordClk
16 pin SOIC 300 mils wide
DS3201-0802 Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
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1 8
AL3201 SCR
Electrical Characteristics and Operating Conditions
Parameter Description Condition Min Electrical Characteristics and Operating Conditions
VDD IDD Gnd FS Temp VOH VOL IOH IOL Supply Voltage Supply Current : SCR Ground Sample rate Temperature Logical Logical Logical Logical "1" output "0" output "1" output "0" output voltage voltage current current Note 3 3.0/4.5 6/9 24 1 0 0.9 VDD -
Typ
3.3/5.0 7/10 0.0 48 25 VDD 0 -
Max
3.6/5.5 8/11 50 1 70 0.05 VDD -8.0 8.0
Units
V mA V kHz C V V mA mA
Outputs (DigOut, SysClk, BitClk, WordClk)
Unloaded Unloaded VDD=5V VO=4.5V VDD=5V VO=0.4V
_______________
__________________________
Inputs (DigIn, Int/Ext, Prog0/Sdata, Prog1/SClk, Prog2, Prog3, Reset) Notes 2,4
VIH Logical "1" input voltage 2.5 VDD V VIL Logical "0" input voltage 0 0.5 V VDD=VIH=5V IIH Logical "1" input current 2 A No pullup pin IIL Logical "0" input current 2 A Pullup pin, Vin=0 IILP Logical "0" input current 83 167 333 A CIN Input Capacitance 2.0 pF Note: 1. Changing the sample rate (by changing the crystal frequency) will change the maximum delay available through the DRAM proportionally. Low sample rates require more refresh instructions. 2. XtalIn, XtalOut are special pins designed to be connected to a crystal. XtalOut is a relatively weak pin (about 0.2 mA) and should not be used to drive external circuits. Instead of using a crystal, XtalIn may be driven by a standard VDD to Gnd logic signal, but the logic levels are not specified. 3. All other voltages are relative to Gnd. 4. Bypass (pin 14) must never exceed 3.6V
Pin Descriptions: AL3201 SCR Pin # Name Pin Type
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DigOut
______________
(*: Pullup to VDD via nominal internal 30k resistor)
Description
Digital serial output for stereo DAC. Internal/external program selection. 1:Internal, 0:External. 12.288MHz crystal input. 12.288MHz crystal output. Internal program select 0 / serial interface data line. Internal program select 1 / serial interface clock line. Internal program select 2. Internal program select 3. Word clock output. Bit clock output. System clock output. Active low reset. Ground connection. Connect 0.1F bypass capacitor to Gnd for internal +3.3V regulator. +5V/+3.3V VDD power pin. Connect 0.1F capacitor to Gnd. Digital serial input from stereo ADC.
Output Input* Input Output Bidirectional* Input* Input* Input* Output Output Output Input Ground Bidirectional Power Input
Int/Ext XtalIn XtalOut Prog0/SData Prog1/SClk Prog2 Prog3 WordClk BitClk SysClk
_____________________
Reset Gnd Bypass VDD DigIn
DS3201-0802
Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com -2-
Block Diagram
Mechanical Specification
Dimensions (Typical) Inches Millimeters 10.31 .406" .295" 7.49 .407" 10.34 .100" 2.50 .008" 0.20 .025" 0.64 .050" 1.27 .017" 0.42 .011" 0.27 .340" 8.66 .033" 0.83
16
9
C
B
1 8
A
A B C D E F G H J K L Notes: 1) Dimension "A" does not include mold flash, protrusions or gate burrs.
K 4 nom
7 nom
D E G F H
J
L
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Internal Programs
The SCR comes with 16 internal ROM programs ready to go, utilizing the skills and techniques of the Alesis Studio Electronics effects processor programmers. By setting the chip to internal mode, the four program pins may be used to select between the different algorithms.
Program List Prg Name
Description
125ms slapback delay for 0* Delay 1 vocals and guitars. Auto-wah guitar effect with 1 Chorus/Room 2 reverb for lead instruments. Warm hall for acoustic 2 Hall 2 guitars, pianos, and vocals. Removes lead vocals from 3 Vocal Cancel many stereo recordings. 190ms delay for percussive 4* Delay 2 arpeggios. Chorus with reverb for 5 Chorus/Room 1 guitars, synths, and pianos. Bright hall reverb for 6 Hall 1 drums, guitars, and vocals. Rotary speaker emulation 7 Rotary Speaker for organs and guitars. Stereo flanger for jet wash 8 Flange effects. Sizzling bright plate reverb 9 Plate 2 for vocals and drums. Hardwood studio for 10 Room 1 acoustic instruments. Classic plate reverb for lead 11 Plate 1 vocals and instruments. Stereo chorus for guitars 12* Chorus and pianos. Short vintage plate reverb 13 Plate 3 for snares and guitars. Ambience for acoustic 14 Room 2 mixes and synth sounds. Warm room for guitars and 15 Room 3 rhythm instruments. Note: The unusual ordering of the programs allows a 16-position rotary switch's Gray code output to be connected to the program pins. The sequence of programs is then Halls 1-2, Rooms 1-3, Plates 1-3, Chorus, Flange, Delays 1-2, Chorus/Rooms 1-2, Vocal Cancel, and Rotary Speaker. * WARNING Programs 0, 4, and 12 do not meet refresh requirements. Do not depend upon these programs working in any application.
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Programming the RAM
Alongside the 16 internal programs is an externally programmable SRAM that is easily accessible through the serial clock and data pins. By setting the chip to external mode, the SClk and SData pins become available for serial communication. Except for its external programmability, there is no functional difference between the SRAM and the internal ROMs. Memory Map Addr
0:127 128 129
The first four instructions in the WCS RAM set the parameters for the four LFOs. The sinusoid generated by the LFOs is of the formula Asin(nF/M) or Acos(nF/M), where n is the time index, F/M = 2f/FS, M is the maximum internal value, f is the selected frequency, and FS is the sampling frequency. Thus the frequency extrema are: f fmin fmax = (F/M) FS/(2) = (0x1/0x3ffff) (48kHz)/(2) = 0.029Hz
Name
Name LFO Coefficients MAC Instructions
Addr WCS RAM 0:3 4:127 Control/Status 0
Control/Status 1
A simple assembly language is available for writing programs. With the assembler and loader software available from the Alesis Semiconductor website, programs may be developed on the PC and downloaded into the chip. Please refer to the assembly language guide for a full description. LFO Coefficient Word Bit # Description
31 30 P: Pitch shift mode select (S must be set).
1
29:28
27:15
S: Sine/triangle select. 1:Triangle; 0: Sine. X[1:0] Xfade X[1:0]: Crossfade 11 1/16 coefficient select. Value indicates the fraction of a 10 1/8 half sawtooth period 01 1/2 used in crossfading. 00 1 F[12:0]: Frequency coefficient, unsigned.
14:0 A[14:0]: Amplitude coefficient, unsigned. Note: If set, the output waveform is a sawtooth with double the triangle wave's frequency. Sawtooth SIN Sawtooth COS Crossfade 1 Crossfade 1/2 Crossfade 1/8
= (0x1fff/0x3ffff) (48kHz)/(2) = 239Hz Triangle waves are generated by incrementally adding or subtracting 0x400000*F/M (= 222*F/M) from the maximum internal negative or positive value respectively. Its frequency extrema are then: f = # Samples / # Steps = FS / (4 Max/Increment) = FS / (4 0x7fffff/(222*F/M)) fmin = 48kHz / (8/(0x1/0x3ffff)) = 0.023Hz fmax = 48kHz / (8/(0x1fff/0x3ffff)) = 187Hz When chorus instructions are used, addresses are offset by the output an LFO. The range of this offset is plus and minus A/8 samples, or A/4 samples total. Following the 4 LFO coefficient words are 124 MAC instruction words. These instructions allow the manipulation of the DRAM and the waveforms generated by the LFOs. A good NOP instruction is 0x00030000. This instruction preserves the value in all registers, and is the NOP executed in the MAC during the first four ticks of every sample period while the LFO coefficients are loaded. By judiciously choosing the LFO frequency and waveform with which to sweep through the DRAM, it is possible to generate pitch shifts, flanges, choruses, reverbs, and other effects. Please see application notes for descriptions and examples.
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MAC Instruction Word Bit # Description
31 S: Sign bit for multiplier coefficient. C[7:1]: Multiplier coefficient, 2's complement. C[7:0]: Chorus instruction. Only the 7 MSBs are used as multiplier coefficients. The LSB is used in chorus mode. If I[5] is set, C[7:0] is: C Description Chorus/Xfade select: 1: Pass LFO address to address generator & select chorus coefficient. 7 0: Mask LFO address to address generator & select crossfade coefficient. 1's complement the LFO address sign 6 bit. 1 5 1's complement the LFO coefficient. 4 1's complement the LFO address. LFO latch. 1: Latch in new LFO data; 3 0: Hold last LFO data. 2 2:1 LFO select. 0 LFO sine/cosine select. 1: Cos; 0: Sin. W: Write select. 3, 4 I[5:0]: Instruction field. I Description Chorus select (When set, MAC coefficient is LFO block output, LFO 5 address offset added to DRAM address). 4 Clock register C. 3 3 Clock register B. 4 2 Reserved - set to zero. I[1:0] Instruction MAC 11 Acc = Prod + Acc 6 product 1:0 10 Acc = Prod + C 3 instruc01 Acc = Prod + B 5 tion. 00 Acc = Prod + 0 A[15:0]: Multiplicand address. 7, 8 (Currently only lower 15 bits used; reserve MSB for future expansion.) Address 0x0000 = LeftIn/Out; Address 0x0001 = RightIn/Out.
5.
6. 7. 8.
30:23
Register B, if clocked at the end of the tick, will store the value of the current tick's multiplicand. When a read is executed, B latches LeftIn, RightIn, or DRAM. When a write is executed, B latches the accumulator from the last tick. The accumulator contains the result from the last instruction tick, and is updated at the end of the current instruction tick. The internal DRAM address offset automatically decrements by 1 every word clock period. Because addresses 0x0000 and 0x0001 are being used to access the left and right channels, those DRAM memory locations may not be directly written to or read from.
22
21:16
15:0
Notes: 1. This complement is only for the MSB, and signextension bits are not affected. 2. Upon latching new data, the LFO registers will store the lower or upper LFO pairs' sinusoid/triangle waves, and the lower or upper LFO pairs' crossfade coefficient. I.e. there are two pairs of registers; LFO 0/1's sinusoid /triangle/crossfade will be latched together, and LFO 2/3's sinusoid/triangle/crossfade will be latched together. 3. The LeftOut, RightOut, and C registers are in parallel with the accumulator, and will contain the same value as the accumulator if clocked at the end of the tick. 4. A write to DRAM stores the last tick's results into address A. Writes to LeftOut or RightOut should use the Acc = Product + Acc instruction with the multiplier coefficient set to 0 to pass all bits unaltered.
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Control/Status Word 0 Bit # Description
31:30 29:16 15:11 10 9 8 7 6 5 4 Reserved. Set to zero. B[13:0]: DRAM read data.
1
3
2 1 0
Reserved. Set to zero. O: MAC overflow. Self-clears after read. Read only. P: Self test pass. Read only. R: Ready indication. Read/write/test/clear complete. M: DigOut mute in external mode. Resets to 1. Z: DRAM zero. Initiates zeroing cycles until deasserted. Resets to 0. 2, 3, 4, 5, 6 X: DRAM zero cancel. Prevents zeroing circuitry from running until deasserted. Overrides Z. Resets to 0. 3 L: LFO reset pulse. Resets LFO internal status registers and clears overflow flag. Self clearing. Resets to 0. I: Instruction RAM direct mode. Resets to 1. 1: Instructions are written/read as soon as received; 0: Instructions are written/read when the address counter rolls around to matching address. 7 Reserved. Set to zero. S[1]: DRAM self test pattern select. 1: Load DRAM with 2AAA/1555 checkerboard; 0: Load DRAM with 1555/2AAA checkerboard. S[0]: DRAM self test initiate. Self-clears after test completion. Resets to 0. 2, 3, 6, 8, 9
8. 9.
its execution. Otherwise reads and writes to the Instruction RAM will usurp the address bus to the RAM and cause address jumps in the instruction sequence. With I deasserted, reads and writes to each address may take up to one word clock period to complete. Thus during continuous writes, the start of each instruction word should be at least one word clock period apart, and during reads the serial clock should wait 1 word clock after the address before continuing. The DRAM self test cycle will run to completion even if S[0] is deasserted. It may not be cancelled. A DRAM self test cycle takes approximately 10.66ms to complete with a 12MHz crystal.
Control/Status Word 1 Bit # Description
R: Read select. Read data from DRAM address A[15:0] and put data in B of 31 control/status word 0. Self-clears after completion. W: Write select. Write data D[13:0] to DRAM 30 address A[15:0]. Self-clears after completion. 29:16 D[13:0]: DRAM write data. A[15:0]: DRAM address. The MSB is unused 15:0 and reserved for future expansion. Note: Reading and writing DRAM will usurp DRAM access for one cycle, possibly disrupting proper code execution.
Notes: 1. The floating point format used in the DRAM is: E[2:0].S.F[9:0], where E is the exponent, S is the sign bit, and F is the fractional portion. The expansion of the floating point into fixed point is as follows: If E<7, S E*S !S FFFFFFFFFF (8-E)*0 (where E*S means E number of S bits). If E=7, S SSSSSSS FFFFFFFFFF 00. This method encodes one extra bit for sign extensions less than 7 bits. 2. The DRAM zeroing circuitry and DRAM self test circuitry share gates; do not turn more than one on at a time. 3. The DRAM zeroing cycle will run to completion even if Z deasserted. Only the X bit may cancel it mid-cycle. Until the cycle ends, self test results will be inaccurate. Thus do not deassert Z and assert S[0] at the same time. Rather, assert X and S[0] at the same time. Note that Z does not self-clear, and will affect both internal and external mode. 4. After a DRAM zeroing cycle has completed, do not start another for one word clock period. 5. A DRAM zeroing cycle takes approximately 5.33ms to complete with a 12MHz crystal. 6. During DRAM zeroing and test cycles, reads and writes to the DRAM are ignored. 7. For dynamically changing programs, deassert I so that changing the program does not interrupt
Other notes: 1. When in internal mode, program changes will start a DRAM zero cycle. 2. Resets always start a DRAM zero cycle. 3. To meet refresh requirements below 70 C, access each address (modulo 1024) every 1.34 ms. If program code doesn't do this, then (at 48 kHz) read 16 locations each cycle spaced 1024/16 = 64 addresses apart, to meet refresh requirements. (For instance, addresses 0x0002, 0x0042, ..., 0x03C2.) 4. ROMs may not be read due to the serial interface becoming the program select interface when in internal mode. 5. Use of Reset is mandatory to obtain proper operation of the AL3201.
The 4 word formats: LFO, MAC, CS0, CS1 LFO: PSXXFFFF FFFFFFFF FAAAAAAA AAAAAAAA MAC: SCCCCCCC CWIIIIII AAAAAAAA AAAAAAAA CS0: --BBBBBB BBBBBBBB -----OPR MZXLI-SS CS1: RWDDDDDD DDDDDDDD AAAAAAAA AAAAAAAA
DS3201-0802
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Serial Interface Format
The basic format for the micro serial interface is: Attn Sel R/W A7 A6 A5 A4 A3 A2 A1 A0 DN DN-1 DN-2 ... D2 D1 D0 Attn Desel Attn: Sel/Desel: R/W: A 0-1-0 is used to signal attention/start. 0:Select; 1:Deselect. A7 - A0: 0:Read; 1:Write DN - D0:
2. 3.
Write mode only
Address Data
Notes: 1. There is a short period of High-Z during a read between A0 and the first data bit shifted out. This period must be at least 5 system clocks long, 1 word clock long if not in direct mode (CS0[3]).
As long as data is being sent during a write, the address will be automatically incremented. Therefore only a start address need be sent. The phase of the clock is unimportant.
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DigIn/DigOut Interface Format
Suggested Connections
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NOTICE
Alesis Semiconductor reserves the right to make changes to their products or to discontinue any product or service without notice. All products are sold subject to terms and conditions of sale supplied at the time of order acknowledgement. Alesis Semiconductor assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Information contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, no responsibility is assumed for inaccuracies. Alesis Semiconductor products are not designed for use in applications which involve potential risks of death, personal injury, or severe property or environmental damage or life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. All trademarks and registered trademarks are property of their respective owners.
Contact Information: Alesis Semiconductor 12555 Jefferson Blvd., Suite 285 Los Angeles, CA 90066 Phone: (310) 301-0780 Fax: (310) 306-1551 Email: sales@alesis-semi.com
Copyright 2002 Alesis Semiconductor Datasheet August 2002
Reproduction, in part or in whole, without the prior written consent of Alesis Semiconductor is prohibited.
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